Everything related to Gate 2017 Electronics and Communication Engineering EC
Can someone help me to prepare for gate 17? Has anyone started preparation?
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any body have gate 2016 test series solution ECE of made easy ??
explian A sequential circuit outputs a ONE when an even number (> 0) of one's are input; otherwise the output is ZERO. The minimum number of states required is
A 2 MHz signal is applied to the input of a J-K lip-lop which is operating in the 'toggle' mode. The frequency of the signal at the output will be
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Does anyone has solved solution for GATE 30th Jan 2016 Shift 1 ? plz share if u hav...
What should be the marks needed by a PWD candidate for PSUs and IITs ?
Can anyone please give the give the phase margin of the system shown in figure. Please give the explanation as well.
HAL has openings for Management trainee and Design trainee. Can anyone tell me the difference between these two? which one to apply for?
How was the exam? How difficult the exam was? Any issue at the examination centre or with computer?
Guys.there was on qus on control.. s*4+s*2+1.. isme poles puchha tha?? Kya ans hoga??
Do u guys remeber morning sessn me netwrk ka questn tha.. time nikaalna tha at i=2 pe..??.. RL ckt tha..
answer for the question about contorus (altitudes) [general aptitude] in morning session
Please guys discuss the answers of afternoon session.